1. Field of the Invention
The present invention relates to an output buffer and a source driver using the same, and more particularly, to the output buffer enhancing the speeds of switching an output voltage of the output buffer to be low level and high level.
2. Description of Related Art
The source driver is an important component in the driving system of the display device, which is used for converting a digital video signal to a driving voltage and providing the driving voltage to a pixel electrode in association with a certain enabled scan line. The driving voltages provided to the pixel electrode are not as good as expected because of the panel loading effect and the process variation so that the source driver utilizes the output buffers to enhance the driving abilities of its driving channels.
FIG. 1A is a circuit diagram of a conventional output buffer. Referring to FIG. 1, the output buffer 100a includes the transistors Mn1 through Mn7, wherein the transistors Mn1, Mn2, Mn3, and Mn6 are N-type transistors and the transistors Mn4, Mn5, and Mn7 are P-type transistors. The output buffer 100a applied to the source driver is a unity gain output buffer so that the output terminal Vout1 of the output buffer 100a may be coupled to the input terminal Vn−. An N-type differential input pair is composed of the transistors Mn2 and Mn3. The transistor Mn1 serves as a current source properly biased by the bias voltage Vb1. The currents In2 flowing through the transistor Mn2 is determined by the input signal at the input terminal Vn−, while the current In3 flowing through the transistor Mn3 is determined by the input signal at the input terminal Vn+.
If the signal of the input terminal Vn+is greater than the signal of the input terminal Vn−, the current In3 is greater than the current In2 so that the voltage of the first source/drain D3 of the transistor Mn3 may be decreased to conduct the transistor Mn7. The output buffer 100a develops a charging path from the power voltage VDD, to the output terminal Vout1 through the conducted transistor Mn7, so as to increase the voltage of output terminal Vout1. If the signal of the input terminal Vn+is less than the signal of the input terminal Vn−, the current In3 is less than the current In2 so that the voltage of the first source/drain D3 of the transistor Mn3 may be increased to make the transistor Mn7 not conduct. The transistor Mn6 is biased by the bias voltage Vb1, and develops a discharging path for decreasing the voltage of the output terminal Vout1. However, the bias voltage Vb1 is a fixed voltage so that the discharging current flowing through the conducted transistor Mn6 is restricted. This kind of output buffer 100a has better charging ability, but its discharging ability is limited. In other words, the speed of an output voltage of the output buffer 100a changing from high level to low level is slower than that changing from low level to high level.
FIG. 1B is another circuit diagram of a conventional output buffer. Referring to FIG. 1B, the output buffer 100b includes the transistors Mp1 through Mp7, wherein the transistor Mp1, Mp2, Mp3, and Mp7 are P-type transistors and the transistors Mp4, Mp5, and Mp6 are N-type transistors. The transistor Mp1 serves as a current source based on the bias voltage Vb2. The current Ip2 is determined by the signals of the input terminal Vp−, while the current Ip3 is determined by the signal of the input terminal Vp+. When the signal of the input terminal Vp+ is less than the signal of the input terminal Vp−, the current Ip3 is increased to conduct the transistor Mp6, so as to develop a discharge path to pull low the voltage at the output terminal Vout2. Besides, when the signal of the input terminal Vp+ is greater than the signal of the input terminal Vp−, the current Ip3 is decreased to make the transistor Mp6 not conduct, and the transistor Mp7, which is conducted by the bias voltage Vb2, develops a charging path. However, this kind of output buffer 100b has better discharging ability, but its charging ability is limited since the bias voltage Vb2 is a fixed voltage. As compared with the output buffer 100a in FIG. 1A, the speed of an output voltage of the output buffer 100b changing from low level to high low level is slower than that changing from high level to low level.
Therefore it is necessary to develop an output buffer with good charging and discharging ability.